The present invention relates to a computer system having a system clock signal which can operate at different speeds in different systems, and more particularly, relates to a mechanism and method for detecting and deterring over-clocking of such a system clock signal in a computer system.
A typical computer system includes a processor subsystem of one or more microprocessors such as Intel(copyright) i386, i486, Celeron(trademark) or Pentium(copyright) processors, a memory subsystem, one or more chipsets provided to support different types of host processors for different platforms such as desktops, personal computers (PC), servers, workstations and mobile platforms, and to provide an interface with a plurality of input/output (I/O) devices. Chipsets may integrate a large amount of I/O bus interface circuitry and other circuitry onto only a few chips. Examples of such chipsets may include Intel(copyright) 430, 440 and 450 series chipsets, and more recently Intel(copyright) 810 and 8XX series chipsets. These chipsets may implement the I/O bus interface circuitry, timer, real-time clock (RTC), direct memory access (DMA) controller, and other additional functionality such as, for example, integrated power and thermal management with quick resume capabilities and random seed number generation for security applications such as cryptography, digital signatures, and protected communication protocols.
For many purposes, these chipsets need to know the system (processor) clock frequency used for proper operations. The system (processor) clock frequency is the frequency of a clock signal upon which all synchronous operations on the system bus are timed. The system clock (operating) speed can vary widely and may be rated differently by processor manufacturers for different processors. Currently, system clock (operating) speeds of host processors can vary from 66 MHz to about 500 MHz. Host processors may be rated at a particular clock frequency based on their ability to operate without errors. Typically, processor manufacturers may be very conservative when rating such a clock frequency. For example, a processor which successfully operates during tests at 333 MHz may be only intentionally rated (marked) at only 133 MHz, 150 MHz, 166 MHz, 200 MHz or 250 MHz for different market reasons.
Since most processors can be clocked at frequencies significantly greater than the rated (marked) clock frequencies, there may be a problem with resellers and/or distributors remarking processors at higher frequencies and then selling the processors as the higher speed part to charge for resale at higher prices. This is possible because the system (processor) clock speed may be initialized and set by jumpers from the motherboard at reset. As a result, unscrupulous resellers and/or distributors may purchase less expensive processors that are rated at lower clock frequencies and then remark those processors at higher clock frequencies, a procedure known as over-clocking (operate the processor at a clock frequency greater than the originally rated frequency) for resale at higher prices.
Over-clocking a system (processor) clock frequency may also produce several problems. A common problem of over-clocking relates to bit errors and data corruptions. Usually, chipsets and/or hardware components which need the system clock frequency for computing operations may incorrectly interpret electrical signals between xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d due to timing violations. More serious problems of over-clocking relate to advanced chipsets which use a random number generator (RNG) for security applications such as cryptography, digital signatures, and protected communication protocols. If the host processor is over-clocked, the statistically random and non-deterministic numbers from the RNG of the chipsets may no longer be random, and the security applications may be severely compromised.
Over-clocking problem may be solved by tying several processor input pins high or low using pull-up and pull-down resistors to select a maximum clock frequency of a host processor. However, this hard-wiring approach to setting a maximum clock frequency is susceptible to external manipulation by users, resellers and/or distributors. A reseller may reconnect these processor input pins to high or low to select a different clock frequency. As a result, the hardwiring approach to solve the over-clocking problem is not secure. Moreover, the hard-wiring approach is inflexible and cumbersome for processor manufacturers.
Therefore, a need exists for a more secure and mechanism for detecting and effectively deterring (preventing) over-clocking of a system (processor) clock signal so as to prevent resellers, distributors and/or end users from operating the processor at a clock frequency that is greater than a rated clock frequency.
Accordingly, various embodiments of the present invention are directed to a mechanism and method for detecting and deterring over-clocking of a clock signal in a computer system. Such a mechanism may comprise a detection circuit which detects over-clocking of a clock signal based on a reference signal, and a prevention circuit which prevents over-clocking of the clock signal by either disabling operations of the computer system or reducing performance of the computer system in response to detection of over-clocking of the clock signal.